Study programme 2020-2021 | Français | ||
Edge Computing | |||
Programme component of Master's in Electrical Engineering à la Faculty of Engineering |
Students are asked to consult the ECTS course descriptions for each learning activity (AA) to know what special Covid-19 assessment methods are possibly planned for the end of Q3 |
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Code | Type | Head of UE | Department’s contact details | Teacher(s) |
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UI-M2-IRELEC-565-M | Optional UE | VALDERRAMA SAKUYAMA Carlos Alberto | F109 - Electronique et Microélectronique |
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Language of instruction | Language of assessment | HT(*) | HTPE(*) | HTPS(*) | HR(*) | HD(*) | Credits | Weighting | Term |
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| Anglais | 60 | 0 | 0 | 0 | 0 | 5 | 5.00 | 2nd term |
AA Code | Teaching Activity (AA) | HT(*) | HTPE(*) | HTPS(*) | HR(*) | HD(*) | Term | Weighting |
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I-SEMI-114 | Edge Computing | 60 | 0 | 0 | 0 | 0 | Q2 | 100.00% |
Programme component |
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Objectives of Programme's Learning Outcomes
Learning Outcomes of UE
EN. This teaching unit will be in English and broken down into two parts. In the first place, "Embedded Software using Python/SoC", embedded architectures, development tools and the development of applications using high level Python and C ++ languages will be developed, accompanied by application cases in the Domotic, IoT (Internet-of-Things) and Machine Learning domains. The second part, "Edge Computing High Level Synthesis", presents the tools for developing complete System-on-Chips, consisting of programmable and reconfigurable parts, development stages, architecture exploration and optimizations. Master the design of systems, concepts, methodologies and tools of development; from its specification at the system level, through the modeling of the problem, the exploration, analysis and optimization of feasible solutions, until obtaining a system that meets the economic and technical needs. Better understand the advantages and disadvantages of existing solutions, and implementation alternatives, according to a set of evaluation criteria (architecture, development costs, size, performance, energy consumption, etc.).). In a practical aspect, the student must deal with the implementation of a solution, partial or complete (including software, operating system, or development of IP components - intellectual Property - off-the-shelf -COTS) all using programmable and reconfigurable technologies and development tools commonly available in the industry.
Content of UE
Embedded Software using Python/SoC
EN. The emergence of the Python Productivity for Zynq (PYNQ) development environment based on Jupyter notebooks solves FPGA programmability issues. With a development board specifically designed to support PYNQ, developers with little FPGA experience can quickly implement designs that can take full advantage of FPGA performance to accelerate applications involving compute intensive tasks for applications such as Home Automation, IoT and Machine Learning. The basic programming of FPGAs is done with 2 possible languages: Verilog and VHDL. VHDL also requires a knowledge of combinational and sequential electronics, unlike Python, an open source language, recognized for its simplicity and very common among programmers.
Architectures. Heterogeneous architectures
Components. The basic components of programmable subsystems
Methodology. The stages of embedded software development (Python and Linux)
Overlays. The development of associated interfaces, peripherals and drivers
IOPs. Configurable and programmable interfaces
Tools. Development tools and environments (Pynq, Jupyter, PYNQ)
Application cases: development examples: audio interfaces, peripheral interfaces (I2C, UART, Analog, PWM, etc.), Home Automation, IoT, Machine Learning (YOLO, BNN Binary Neural Networks)
Edge Computing High Level Synthesis
EN. This section shows a unified view of hardware and software domains as implementation alternatives based on design exploration and metrics. The objective of the course is to learn how to develop a complete programmable and configurable system called System-on-Chip (SoC). These systems use high-level languages, such as Python and C/C++. However, some features, such as intensive computing, peripheral drivers, signal processing, or real-time control, require hardware accelerators. These accelerators and their associated programmable interfaces are the result of development steps giving access to reconfigurable electronics, or FPGAs. Accelerators and their associated programmable interfaces are the result of development steps giving access to reconfigurable electronics, or FPGAs. We do not go through combinational and sequential logic to program an FPGA; high-level tools such as SDSoC and HLS (High Level Synthesis) are available. A higher level of programming is performed to achieve a hardware architecture in an FPGA circuit. The FPGA circuit can be a Zybo, Pynq or Zed Board, where advanced applications such as image processing are developed. The system will be considered as a system-on-chip or SoC, in which, the execution of Python applications can be accelerated by reconfigurable hardware accelerators. The course explores the different trends, components and alternatives according to the final objective. The system level design is introduced by first a description of the different components involved, since integrated circuits design and usage up to software, processors and custom hardware processors. It also covers design methodologies, optimization techniques and test environments. The course is complemented by practical exercises and laboratory sessions using state of the art technologies, technologies trends and design challenges.
SoC architecture exploration. Design Analysis and implementation alternatives.
Improving performance. Optimization strategies. Improving Resources.
Interface Synthesis. Hardware/software encapsulation and IO protocols.
Verification and validation steps. Prototyping, scheduling, simulation and emulation.
IP creation. Components creation and utilization.
Coding considerations.
Prior Experience
Digital Electronics, Embedded Systems, Microprocessors
Type of Assessment for UE in Q2
Q2 UE Assessment Comments
Edge Computing (28508) UI-M2-IRELEC-565-M: Total 2nd session (2nd quarter - June): 100%. Practical laboratory work TP 10%; Practical test of laboratory results outside the examination session 10%; Final deliverables for Personal Projects / Works (report, prototype, model, plan, ...) 45%. Final presentation of Projects / Personal work 35%. Additional comments introduced by the teacher: practical test of laboratory results outside the exam session: at least 1 week after the last practical work session, separation of the evaluations according to the grouping or duplication of the practical work according to the purposes; delivery of the results of the practical work and final delivery of the deliverable for the project / personal work (report, prototype, model, plan, etc.): one week before the date of the first exam; final presentation of the Project / Personal work in session/examination period: separation of evaluations according to the groups or duplication of practical work according to specialties; presentations in groups of 2-3 students, maximum 30 'of presentations per group, maximum 6 presentations in groups of 4 hours.
Type of Assessment for UE in Q3
Q3 UE Assessment Comments
Edge Computing (28508) UI-M2-IRELEC-565-M : Total 2nd session 100%: Final deliverables for Projects / Personal Works (report, prototype, model, plan, ...) 60%. Final Presentation of Projects / Personal Works: 40%. Additional comments : final delivery of Project / Personal work results (report, prototype, model, plan, ...) one week before the date of the first examination; final Presentation of Project/Personal work in examination session/period: separation of the evaluations according to groups or duplication of TPs per specialties, presentations in groups of 2-3 students, maximum 30 'presentations per group, maximum 6 presentations per 4-hour evaluation
Type of Teaching Activity/Activities
AA | Type of Teaching Activity/Activities |
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I-SEMI-114 |
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Mode of delivery
AA | Mode of delivery |
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I-SEMI-114 |
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Required Reading
AA | |
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I-SEMI-114 |
Required Learning Resources/Tools
AA | Required Learning Resources/Tools |
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I-SEMI-114 | EN. Tutorials available on GitHub and Xilinx Vivado Pynq and Vitis |
Recommended Reading
AA | |
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I-SEMI-114 |
Recommended Learning Resources/Tools
AA | Recommended Learning Resources/Tools |
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I-SEMI-114 | Not applicable |
Other Recommended Reading
AA | Other Recommended Reading |
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I-SEMI-114 | Not applicable |
Grade Deferrals of AAs from one year to the next
AA | Grade Deferrals of AAs from one year to the next |
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I-SEMI-114 | Authorized |