Organisational arrangements for the end of Q2 2020-2021 assessments (Covid-19) online or face-to-face (according to assessment schedule)

• Oral exam (questions and answers, presentation of individual or group work, comment and argument about a written text...)
• Production of individual or group work, essay, report, dissertation...

Description of the modifications to the Q2 2020-2021 assessment procedures (Covid-19) online or face-to-face (according to assessment schedule)

Final delivery of deliverable for Project / Personal work (report, prototype, model, plan): one week before the date of the first examination.
Final presentation of Project / Personal work in session/examination period: maximum 30 'of presentations per group, maximum 6 presentations per 4-hour exams. Covid-19: Via Teams.

Content of Learning Activity

Embedded Software using Python/SoC 
EN. The emergence of the Python Productivity for Zynq (PYNQ) development environment based on Jupyter notebooks solves FPGA programmability issues. With a development board specifically designed to support PYNQ, developers with little FPGA experience can quickly implement designs that can take full advantage of FPGA performance to accelerate applications involving compute intensive tasks for applications such as Home Automation, IoT and Machine Learning. The basic programming of FPGAs is done with 2 possible languages: Verilog and VHDL. VHDL also requires a knowledge of combinational and sequential electronics, unlike Python, an open source language, recognized for its simplicity and very common among programmers.
Architectures. Heterogeneous architectures
Components. The basic components of programmable subsystems
Methodology. The stages of embedded software development (Python and Linux)
Overlays. The development of associated interfaces, peripherals and drivers
IOPs. Configurable and programmable interfaces
Tools. Development tools and environments (Pynq, Jupyter, PYNQ)
Application cases: development examples: audio interfaces, peripheral interfaces (I2C, UART, Analog, PWM, etc.), Home Automation, IoT, Machine Learning (YOLO, BNN Binary Neural Networks)
Edge Computing High Level Synthesis
EN. This section shows a unified view of hardware and software domains as implementation alternatives based on design exploration and metrics.  The objective of the course is to learn how to develop a complete programmable and configurable system called System-on-Chip (SoC). These systems use high-level languages, such as Python and C/C++. However, some features, such as intensive computing, peripheral drivers, signal processing, or real-time control, require hardware accelerators. These accelerators and their associated programmable interfaces are the result of development steps giving access to reconfigurable electronics, or FPGAs. Accelerators and their associated programmable interfaces are the result of development steps giving access to reconfigurable electronics, or FPGAs. We do not go through combinational and sequential logic to program an FPGA; high-level tools such as SDSoC and HLS (High Level Synthesis) are available. A higher level of programming is performed to achieve a hardware architecture in an FPGA circuit. The FPGA circuit can be a Zybo, Pynq or Zed Board, where advanced applications such as image processing are developed. The system will be considered as a system-on-chip or SoC, in which, the execution of Python applications can be accelerated by reconfigurable hardware accelerators. The course explores the different trends, components and alternatives according to the final objective. The system level design is introduced by first a description of the different components involved, since integrated circuits design and usage up to software, processors and custom hardware processors. It also covers design methodologies, optimization techniques and test environments. The course is complemented by practical exercises and laboratory sessions using state of the art technologies, technologies trends and design challenges.
SoC architecture exploration. Design Analysis and implementation alternatives.
Improving performance. Optimization strategies. Improving Resources.
Interface Synthesis. Hardware/software encapsulation and IO protocols.
Verification and validation steps. Prototyping, scheduling, simulation and emulation.
IP creation. Components creation and utilization.
Coding considerations. 

Required Learning Resources/Tools

EN. Tutorials available on GitHub and Xilinx Vivado Pynq and Vitis

Recommended Learning Resources/Tools

Not applicable

Other Recommended Reading

Not applicable

Mode of delivery

• Mixed

Type of Teaching Activity/Activities

• Cours magistraux
• Conférences

Evaluations

The assessment methods of the Learning Activity (AA) are specified in the course description of the corresponding Educational Component (UE)