Code | Type | Head of UE | Department’s contact details | Teacher(s) |
---|---|---|---|---|
UI-B3-IRCIVI-202-M | Compulsory UE | HANCQ Joel | F105 - Théorie des circuits et Traitement du signal |
Language of instruction | Language of assessment | HT(*) | HTPE(*) | HTPS(*) | HR(*) | HD(*) | Credits | Weighting | Term |
---|---|---|---|---|---|---|---|---|---|
Français | 0 | 0 | 0 | 0 | 0 | 5 | 5 |
AA Code | Teaching Activity (AA) | HT(*) | HTPE(*) | HTPS(*) | HR(*) | HD(*) | Term | Weighting |
---|---|---|---|---|---|---|---|---|
I-TCTS-020 | 60% | |||||||
I-TCTS-021 | 20% | |||||||
I-TCTS-022 | 20% |
Objectives of general skills
- Implement an engineering approach dealing with a set problem taking into account technical, economic and environmental constraints
- Understand the stages of an engineering approach
- Identify and describe the problem to be solved and the functional need (of prospective clients) to be met considering the state of technology
- Design, evaluate and optimise solutions addressing the problem
- Implement a chosen solution in the form of a drawing, a schema, a plan, a model, a prototype, software and/or digital model
- Understand the theoretical and methodological fundamentals in science and engineering to solve problems involving these disciplines
- Identify, describe and explain the basic principles of engineering particularly in their specialising field
- Select and rigorously apply knowledge, tools and methods in sciences and engineering to solve problems involving these disciplines
- Collaborate, work in a team
- Interact effectively with other students to carry out collaborative projects.
UE's Learning outcomes
Study any logic system and present a critical analysis of it (first part: knowledge of basic components and their association);
Use the presented approaches like guides and implement them in a project who shows his ability to find a solution to a given problem (second part: for different application areas, specification of a hardware with current software tools (VHDL compilers).
UE Content
Generalities including Boolean algebra, simplification methods,
Logic components,
Analysis and synthesis (combinational and sequential),
The Grafcet;
Methods for specific application areas (Petri Nets, statecharts, algorithmic state machines,
Binary information processing and protection,
Introduction to VHDL language.
Prior experience
Not applicable
Term 1 for Integrated Assessment - type
- Presentation and works
- Oral examination
- Quoted exercices
Term 2 for Integrated Assessment - type
- N/A
Term 3 for Integrated Assessment - type
- Oral examination
Type of Teaching Activity/Activities
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Mode of delivery
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Required Reading
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Required Learning Resources/Tools
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Recommended Reading
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Recommended Learning Resources/Tools
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Other Recommended Reading
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Term 1 Assessment - type
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Term 1 Assessment - comments
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Resit Assessment - Term 1 (B1BA1) - type
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Resit Assessment - Term 1 (B1BA1) - Comments
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Term 2 Assessment - type
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Term 2 Assessment - comments
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Term 3 Assessment - type
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |
Term 3 Assessment - comments
AA | |
---|---|
I-TCTS-020 | |
I-TCTS-021 | |
I-TCTS-022 |